As integrated circuit fabrication technology advances, the physical size of an integrated circuit device becomes progressively smaller. A given wafer size can now produce more integrated circuit devices per wafer without increasing a cost of wafer fabrication. One group of technical disciplines is aimed at packaging the devices. As devices become more complex and need to be integrated with additional devices, a universal interconnection scheme becomes more difficult.
Typically, a semiconductor device has fixed input/output (I/O) lines and interconnection with an external package can be difficult. This difficulty may lead to a redesign of an entire integrated circuit to avoid long lead wires from the device to the package. Additionally, any lead lines that cross over each other have a potential for developing an electrical short. Therefore, the interconnection of semiconductor devices with device packages is a major challenge in the art.
The integrated circuit devices are mounted on a surface of a mounting substrate and layers of interconnect lines and vias are formed that connect the devices to surrounding circuitry. Many different packaging approaches are known and have been used for mounting and interconnecting semiconductor devices, such as Dual-In-Line Packages (DIP), Pin Grid Arrays (PGA), Plastic Leaded Chip Carriers (PLCC) and Quad Flat Packages (QFP).
A maximum allowable bond wire length in package assembly is typically in a 3.8 mm-4.6 mm (150 mil-180 mil) range. However, with a smaller integrated circuit die size, a distance between the die on the package lead bond post increases since the standard packages tend to remain the same size. This increase in distance between the integrated circuit package and the integrated circuit die can sometimes result in wire leads in excess of 5 mm (200 mil) or more. This long lead length can create assembly defects of wire-sweep during a molding operation resulting in potential electrical shorts between adjacent lead wires.
Currently, one solution is to convert the package into a stack-die configuration. In this case, a bottom die has metal pads patterned to be used as “jumper” pads. A lead wire would be bonded from a top integrated circuit die onto the bottom jumper die and then, in turn, to the package lead. This breaks up the long wire into two shorter segments. However, this solution also requires design and fabrication of the jumper die. The jumper die, together with a stack die assembly, is a significant cost to a final assembled package.
FIG. 1A shows a cross-section of a typical integrated circuit die 101 mounted into a lead frame package 100 (for example, a QFP). The lead frame package 100 includes a die-attach pad 103, die-attach adhesive 105, a plurality of lead frames 107, electrically-insulating adhesive 109, and a plurality of wire leads 111A. Once the plurality of bond wire leads 111A are connected from the integrated circuit die 101 to the plurality of lead frames 107, a mold compound 113 is used to encapsulate and complete the lead frame package 100.
FIG. 1B shows a bottom jumper die 115. A plurality of bond wire leads 111B are connected from the integrated circuit die 101 to the bottom jumper die 115 and then to the plurality of lead frames 107, thus eliminating overly long bond wires.
An integrated circuit die, for example, a logic die, with 700 circuits and three layers of wiring has approximately 5 m of aluminum wiring on a chip less than 5 mm square. There are over 17,000 via connections from level to level through an insulator film of SiO2. Yet, the conductor capacity in the die greatly lags behind the densification of the silicon devices. Most of the area of the die (approximately two-thirds), still serves as a platform for wiring.
Therefore, what is needed is a is way to provide for flexible wiring techniques between semiconductor devices and packages while avoiding problems associated with long lead lines and potentially shorted devices. Additionally, a universal package which may be used with a variety of different semiconductor devices is desirable.